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Job Area: Administrative Req #: N1822377 Job Title: Sr. Secretary Location: California - San Diego Post Date: 12/2/2008 5:18:06 PM Regular/Temp: R # Positions: 1
Education: Completion of high school diploma required. Bachelor's degree preferred.
Role: - Support executive and management staff - Screen, receive, route and answer calls - Arrange multiple meetings, conference bridges, appointments, luncheons and events for a large group of Product Managers. - Respond to inquiries from company executives - Create and process expense reports and petty cash requests - Purchase office supplies, food and refreshments for meetings and/or luncheons. Balance a credit card at the end of each month. - Responsible for maintaining office files - Arrange for shipping from simple shipping to complex international shipments. - Able to work independently and without a lot of direct supervision - Must maintain strict confidentiality on sensitive issues - Responsible for arranging international travel. Arrange for business visa for many different nationalities. - Help with secretarial coverage when they are on vacation - Arrange guest offices for QC employees from other offices. - Partner and work with other secretaries and groups in different locations.
Skills: - Minimum of five years of prior secretarial experience. - Comprehensive knowledge of departmental/organizational practices, polices and procedures. - Thorough knowledge of Outlook/Eudora, Microsoft Word & Excel, and PowerPoint. - Strong verbal and written communications skills in working with complex matters and senior level personnel inside and outside of the company. - Ability to operate in a professional environment. - Must be able to prioritize work load and multi-task. - Must be able to keep track and remind Product Managers about follow up items. - Strong customer service skills, well organized, ability to adjust to multiple deadlines, attention to detail and work well with different personalities.
Job Area: Administrative Req #: N1823171 Job Title: Executive Secretary, (Temp to Hire) - Qualcomm Enterprise Services Location: California - San Diego Post Date: 12/2/2008 3:55:58 PM Regular/Temp: R # Positions: 1
Education: High School Diploma, Associate's degree in Business Administration or equivalent experience preferred.
$
Role: This is a Temp-to-Hire position.
Provides diverse and complex assistance and support to Vice President Operations and Vice President of Career Relations. Exposure to confidential information and upper management levels requires use of tact and diplomacy on a regular basis. Sound judgment and detail-oriented are must-have skills. Writes, tracks and maintains complex correspondences, memorandums, arranges meetings and travel plans, arranges luncheons, makes and schedules appointments, answers, screens, routes and/or responds to calls, sets up and maintains files, reviews draft and finished documents for accuracy and grammar, orders office supplies. Prepares materials for presentations. Coordinates special projects and compiles information and completes complex reports. Works under minimal supervision.
Skills: Comprehensive reading, writing and math skills required. Minimum of seven years of prior secretarial experience in large (>500 people) organizations. Advanced knowledge of departmental/organizational policies and procedures, company products and programs. Advanced knowledge of Microsoft Outlook, Word, Excel, and PowerPoint. Ability to work in a collaborative, team environment.
Job Area: Engineering - Hardware Req #: G1817694 Job Title: Sr. Package Design Engineer Location: California - San Diego Post Date: 11/25/2008 10:27:45 AM Regular/Temp: R # Positions: 1
Education: Bachelor's degree in Electrical Engineering/Mechanical Engineering required. Master's degree in Electrical Engineering/Materials Science/Mechanical Engineering preferred.
Role: The IC Package Design team within the IC Package Engineering group has an opening for a Design Engineer. This group designs discrete and SiP based high speed digital, RF/Analog and power management IC packages for Qualcomm wireless communication chips sets. Job responsibilities for this position include concept analysis for new products, package assembly design, substrate design, co-design of IC/PCB and documentation of design/manufacturing specifications.
Skills: -3-5 years of package design experience -Excellent written and verbal skills -Knowledge of System-in-Package (SiP) package construction and design requirements -Concept analysis for new product package selection based on requirements for size, performance and cost -Knowledge of assembly and substrate manufacturing processes -Substrate layout skills -Knowledge of the following software: Cadence SiP/APD, Cadence SCM, Cadence First Encounter, CAM350, AutoCAD, Excel, UNIX/Linux -Knowledge of IC floor planning and bump/pad layout -Experience working with Assembly and Substrate suppliers -Mechanical engineering CAD skills a plus -Electrical engineering signal integrity skills a plus
Job Area: Engineering - Hardware Req #: G1817715 Job Title: Circuit/CAD Engineer Location: California - San Diego Post Date: 12/2/2008 11:23:15 AM Regular/Temp: R # Positions: 1
Education: Masters in Electrical Engineering with 2-3 years of industrial experience in the field of VLSI design.
Role: The IP Library team has an opportunity available to work with sub nanometer cutting edge technologies. This group Designs, validates, verifies and characterizes high speed SRAM Memory and SerDes designs for Qualcomm's QCT division. Some other functions of this group also include:
<LI>Development of Single and Multi Port RAM Compilers. <LI>Development of SerDes like MDDI, HDMI, SATA, PCIe <LI>'Memory and High Speed IO' Timing Characterization. <LI>Generation of front and back end views used in typical ASIC flow. <LI>Building test chips to verify the IP. <LI>Produce Test Plans and Test Vectors for Silicon Characterization.
The Engineer working for this team will have the following responsibilities:
<LI>Characterization and generation of timing files for Memory, SERDES and other High Speed IO. <LI>Behavior modeling, Functional and Formal Verifications of designs <LI>Design Validation and Timing Verification of Memory and High Speed IO. <LI>Scripting and Automation work for Validation and Verification of Designs.
Skills: <LI>2 + years of Industrial Experience in using Hspice/Hsim (or any other Industry standard) spice simulators. <LI>Strong Automation skills. Prior Experience in PERL scripting is needed. C/C++ Coding is desired. <LI>Experience in writing Test benches and presenting Test plans. <LI>Experience in tcl scripting is preferred. <LI>Prior experience in characterization of .libs in highly valued. <LI>Understanding of IO and SRAM circuits is desired. MATLAB, SKILL scripting experience are a plus
Job Area: Engineering - Hardware Req #: G1817936 Job Title: Director of IC Design - SERDES Location: California - San Diego Post Date: 11/24/2008 10:41:24 AM Regular/Temp: R # Positions: 1
Education: Bachelors or Master's Degree in Electrical Engineering *
Role: This technical management position is for Director of IC Design engineering to lead our SERDES IP development team & deliver quality low power IPs in state of art CMOS technology nodes for integration into our advanced mobile baseband & consumer products.
We are considering candidates with a proven track record in sub-micron CMOS SERDES developments for the existing industry standards such as HDMI, PCIE, SATA, and XAUI, USB2.0, GbE.
Responsibilities: <LI>Work with Product Design & Marketing to produce roadmaps in response to customer requirements and business trends. <LI>Manage the team and development activities in relationship to current & future product needs <LI>Establish solid Design process, design review & Verification flow for the team to follow & track the progress. <LI>Manage internal cross-functional development & production challenges related to high volume production. <LI>Provide technical leadership and guidance to the organization.
Skills: <LI>A proven track record of achievement and success in driving an engineering team to deliver one of the following SERDES IP in high volume production: USB 2.0, HDMI, PCIE, SATA, XAUI and GbE. <LI>Ability to establish clear goals to direct reports and communicate team's vision, objectives and goals to upper management. <LI>Ability to foster accountability and ownership through leadership by example. <LI>Proven successful track record in people and project management with an engineering team. <LI>Excellent written and verbal communication skills in interactions with customers, and internal development teams. <LI>15+ year's CMOS IC development expertise with 5+ year's senior management experience in a leadership and product ownership role.
Job Area: Engineering - Hardware Req #: G1818478 Job Title: I/O Design Manager Location: California - San Diego Post Date: 12/2/2008 10:16:37 AM Regular/Temp: R # Positions: 1
Education: Bachelors or Masters Degree in Electrical Engineering
Role: This technical management position is to lead our IO design team & deliver quality low power IPs in state of art CMOS technology nodes for Qualcomm advanced mobile baseband & consumer products. We are considering candidates with a proven track record in managing state-of-art CMOS IO designs.
Responsibilities: <LI>Work with Product Design & Marketing to produce roadmaps in response to customer requirements and business trends. <LI>Work with Package engineers and system engineers to meet the design specifications. <LI>Manage the team and development activities in relationship to current & future product needs <LI>Establish solid Design process, design review & Verification flow for the team to follow & track the progress. <LI>Manage internal cross-functional development & production challenges related to high volume production. <LI>Provide technical leadership and guidance to the team.
Skills: <LI>A proven track record of achievement and success in driving an engineering team to deliver IO designs. <LI>Ability to establish clear goals to direct reports and communicate team's vision, objectives and goals to upper management. <LI>Ability to foster accountability and ownership through leadership by example. <LI>Proven successful track record in people and project management with an engineering team. <LI>Excellent written and verbal communication skills in interactions with customers, and internal development teams. <LI>7+ year's CMOS IC development expertise with 3+ year's management experience in a leadership and product ownership role.
Job Area: Engineering - Hardware Req #: G1819469 Job Title: New Grad - Hardware Engineer Location: California - San Diego Post Date: 11/4/2008 12:00:02 AM Regular/Temp: R # Positions: 1
Education: Bachelors, Master's or PhD degree in Electrical Engineering or Computer Engineering. Coursework in the following areas: Circuits and Electronics, Signals and systems, Microelectronic Devices and Circuits, Semiconductor Devices, Feedback systems, Analog Integrated circuits, Digital Integrated Circuits, Digital Signal Processing, Low power analog VLSI.
Role: Ranked #8 by Fortune Magazine's annual '100 Best Companies to Work For' and headquartered in San Diego, QUALCOMM develops, manufactures, markets, licenses, and operates advanced 3G communications systems and products based on its proprietary digital wireless technologies. To ensure that the entire wireless industry is inspired and continues to evolve, innovate and experience success, QUALCOMM develops its technologies and solutions for the purpose of enabling key participants in the wireless value chain.
Role: As a hardware engineer at QUALCOMM, you will work with programmable logic, digital signal processors, microprocessors, and ASICs on high-density circuit cards and gain hands-on knowledge during design validation and system integration. We are also looking for exceptional hardware designers who will design and develop full custom and semi-custom complex digital and analog ICs for wireless network and communication systems.
Positions Include: . Board and FPGA Design . ASIC Digital Design . Mixed Signal Design . RF/Analog/Mixed Signal Design . Design Verification
Skills: Relevant skills include experience with verifying SoC with embedded RISC/DSP processors, communications/ networking ASICs. Verilog or VHDL, C/C++, Tcl/Perl/shell-scripting. RTL design experience and/or strong OO programming experience is also a plus. Knowledge of wireless/wired communications and protocols or graphics/video multi-media is a plus.
Job Area: Engineering - Hardware Req #: G1819981 Job Title: Senior ASIC Product Development Engineer Location: California - San Diego Post Date: 10/16/2008 12:43:01 PM Regular/Temp: R # Positions: 1
Education: BSEE required.
Role: Use your product test skills on cutting edge HP, Teradyne, IMS, etc platforms as well as your hardware (IC and circuit design) skills to bring new IC designs which are fabricated in advance submicron processes into production. Product engineers are responsible for supplier interface, device characterization, statistical correlation/analysis, design for manufacturability/testability, yield enhancement, test time reduction and product cost management.
Skills: Must have minimum of 4 years experience as a Product or Test Engineer in the semiconductor industry performing above functions.
Must have experience developing ATE test programs for high speed interfaces (i.e PCIe, HDMI, SATA,DDR2/3), good understanding of sequential circuits, VLSI manufacturing process/steps, and signal integrity. ASIC ATE experience preferred. Agilent/HP
Job Area: Engineering - Hardware Req #: G1649008 Job Title: ASIC Design/Modem Architect Location: California - San Diego Post Date: 10/18/2008 12:00:03 AM Regular/Temp: R # Positions: 1
Education: Required: Bachelor's, Computer Engineering and/or Electrical Engineering Preferred: Master's, Computer Engineering and/or Electrical Engineering or equivalent experience
Role: QUALCOMM CDMA Technologies (QCT) is the largest provider of 3G chipset and software technology in the world, with chipsets shipped to more than 50 customers and powering the majority of all 3G devices commercially available. QCT partners with nearly 60 3G network operators around the globe and has the largest CDMA engineering team in the wireless industry.
Qualcomm CDMA Technologies is looking for several creative engineers (at all levels) to develop next generation wireless modems (CDMA, UMTS, OFDM, GSM, and etc). Responsible for system architecture definition, and/or RTL implementation.
Skills: Solid understanding of Discrete-time Signal Processing and Digital Communications.
Knowledge of ASIC design including architecture and/or RTL design.
Job Area: Engineering - Hardware Req #: G1794612 Job Title: Emulation/FPGA Engineer Location: California - San Diego Post Date: 10/20/2008 12:00:04 AM Regular/Temp: R # Positions: 1
Education: Bachelor's Degree in Electrical Engineering required, Master's Degree in Electrical Engineering preferred.
Role: QUALCOMM CDMA Technologies (QCT) is the largest provider of 3G chipset and software technology in the world, with chipsets shipped to more than 50 customers and powering the majority of all 3G devices commercially available. QCT partners with nearly 60 3G network operators around the globe and has the largest CDMA engineering team in the wireless industry.
As part of the Emulation Team, you will: <LI>Port ASIC RTL code to FPGA environment. <LI>Work on the synthesis and Place And Route (PAR) the RTL code to custom / off the shelf emulation platforms. <LI>Write various constrain files and perform speed optimization <LI>Work in the lab to debug FPGA builds and perform bring up tasks <LI>Collaborate with ASIC hardware designers to resolve RTL issues <LI>Work with software, AST, and VI (Verification / integration) team in resolving VI / FPGA issues <LI>Work on the Partition of the ASIC RTL code across the custom emulation hardware platforms <LI>Create emulation plans for various MSM projects. <LI>Design new custom emulation hardware platforms. <LI>Contribute to the board design activities. <LI>Lead emulation activities for MSM projects and collect requirements from various customers of the emulation activities. <LI>Work on various emulation specific design activities.
Skills: <LI>Minimum experience of 2 full years working closely with large FPGAs. <LI>Requires a strong digital foundation in design (VHDL), simulation, synthesis (DC), place/route, integration, and debug. <LI>Qualifying candidates should be able to quickly assimilate and refine existing designs; apply test equipment and problem solving skills in the lab; maintain designs under revision control; and actively contribute toward the validation of QCT ASICs using FPGA emulators. <LI>Must be a self-starter and team player with a solid understanding of electrical engineering fundamentals. <LI>High-speed digital board design and/or knowledge of chip verification very desirable. <LI>Mobile phone, Microprocessor, ASIC, or gate array experience beneficial.
Job Area: Engineering - Hardware Req #: G1670810 Job Title: Bench Test Engineer - Mixed Signal Location: California - San Diego Post Date: 11/1/2008 12:00:01 AM Regular/Temp: R # Positions: 1
Education: Required: Bachelor's, Electrical Engineering Preferred: Master's, Electrical Engineering
Role: Entry level Engineer to all levels of Sr Engineer(ie. Sr, Staff, Sr Staff, Principal)
QUALCOMM CDMA Technologies (QCT) is the world leader in supplying integrated circuit solutions for cellular wireless standards and is the number one fabless semiconductor company in the world. The key to QCT's success is the ability to deliver to our customers complete optimized wireless platforms incorporating protocol, hardware, software and support, with high quality, on schedule. The RF/Analog organization within QCT develops all RF, mixed-signal, and analog ICs for these complete wireless platforms.
In order to drive our next phase of growth in cellular, wireless peripherals and 4G, we are expanding our RF/Analog Product Development and Test Engineering group.
The RF/Analog Product Development and Test Engineering group develops test solutions for design verification of highly integrated RF receivers/transmitters/transceivers, power management, analog and mixed signal ASICs designed by QCT. This group has an opening for a Mixed Signal Bench Test Engineer position. Job responsibilities for this position include design and debug of test interface hardware, test methodology implementation, test equipment automation, and device verification/characterization.
Skills: Understanding of electrical engineering concepts and circuit solving skills Working knowledge of ADC, DAC, and general communication measurements (ie INL, DNL, Gain and Offset Error, SFDR, THD+N, ICN, etc) Able to work with common test equipment (oscilloscope, spectrum analyzer, time interval analyzer, logic analyzer, network analyzer, etc) Capable of understanding and modifying LabVIEW test software Knowledge in mixed-signal or analog PCB design including CAD interface Test board design, debug, and development Ability to communicate clearly, organize effectively and document work thoroughly Familiarity with cellular standards such as CDMA2000, 1X-EVDO, WCDMA, UMTS, GSM/GPRS/EDGE, or wireless peripheral standards such as 802.11x WLAN or other OFDM-based systems, GPS, and Bluetooth is desirable.
Job Area: Engineering - Hardware Req #: G1820303 Job Title: ASIC Design Engineer - Security Location: California - San Diego Post Date: 12/2/2008 10:17:09 AM Regular/Temp: R # Positions: 1
Education: Masters Degree in Electrical Engineering preferred
Role: The MSM and CSM design group in QCT is seeking experienced Digital Design Engineers for its San Diego site. The work will expose the designer to a large number of wireless standards, including: 1x CDMA, UMTS, GSM, GPRS, EDGE, 802.11, BT, OFDM, UWB, and others. Additionally, many of our products integrate exciting multi media features, such as H.263, H.264, MPEG, 2D/3D graphics, tv encoding technologies, and digital camera technologies. Low power micro-architecture design techniques are key design point features of these chips. Elegance and efficient verification are valued design techniques. High quality and low cost are all key design points for our products. Leading edge process technologies such as 65nm and 45nm are in design with 65nm products already in production.
Skills: The successful candidate has a strong exposure to security concepts and implementation techniques. Strong familiarity with cryptographic algorithms (SHA, AES, DES), their implementation and use models within high level protocols, is expected. This is a high level, high profile position, requiring interaction with cross-functional teams. The candidate has to be able to identify and evaluate potential security threats, holes, propose countermeasures, understand and interpret government standards (NIST, OMTP). In addition the candidate should have strong knowledge of ASIC design including architecture, verification of integrated system, RTL design, synthesis, and timing closure. Specific experience with DC/PC, Vera, LINT, PTSI, and VHDL are all pluses. Experience with complex SOC integrations, including advanced verification techniques are a must. Design experience and background in low power, high volume applications are desired.
Job Area: Engineering - Hardware Req #: E1820526 Job Title: Design Verification Engineer (ASIC, Vera, C++) - Corp R&D Location: California - San Diego Post Date: 10/24/2008 12:53:23 PM Regular/Temp: R # Positions: 1
Education: Bachelor's degree in Computer Engineering/Electrical Engineering required. Master's degree in Computer Engineering/Electrical Engineering preferred.
Role: Hardware Verification - ASIC Vera C++ / Verification Engineer
Chip verification engineer responsible for designing and developing verification environment components, and writing, executing and debugging tests from testplans or functional specifications. Will work directly with various project teams to assist with the deployment of design for verification methodologies. Verification components to be developed may include bus functional models/transactors/bus interface models, data/transaction and scenario generators, bus monitors, checkers, and coverage models.
Skills: Hardware Verification Engineer - ASIC Verification
Qualifying hardware engineering candidates must possess knowledge of design for verification methodologies. They are expected to be able to articulate how to apply such techniques as assertions, directed random test generation and coverage to full chip verification. IC verification experience should include use of modern verification techniques, tools, and languages. Must be skilled in Vera, Specman-E or, C++/OOP, and have a strong background in data structures and algorithms. Hands-on chip verification experience is required. Chip design experience using industry-standard hardware description languages (Verilog/VHDL) is desired.
Excellent verbal and written presentation/communication skills are mandatory. Strong interest and understanding of design for verification methodologies is required. Must have excellent interpersonal and teamwork skills, strong problem solving skills, and a proven ability to work effectively in a fast-paced environment. Experience with scripting languages, preferably Tcl and perl. The candidate should be familiar with the software development process and related tools on Unix/Linux platforms.
Job Area: Engineering - Hardware Req #: G1820855 Job Title: ASIC Verification / Test Engineer, Vector Translation & Simulation Location: California - San Diego Post Date: 10/8/2008 10:48:04 AM Regular/Temp: R # Positions: 1
Education: Requires a Bachelor's degree in Electrical Engineering, Computer Science or Computer Engineering. Master's degree in Electrical Engineering, Computer Science or Computer Engineering preferred.
Role: The ideal candidate for this position will work with Digital Designers to develop a regression system for SoC verification. The regression system is to be used by all projects to automate chip verification and analysis. This individual will help with functional verification methodology through gate level and timing simulation. Verify test structures through simulation, generate, and process test patterns from design simulation files (EVCD and STIL format) to tester format. In addition this individual will support Test Engineering in the implementation of these patterns and methodologies on Automatic Test Equipment.
Skills: Five plus years in developing Verification solutions including tools and flows in most of the following areas. * Experience with Modelsim, NC-Verilog, VCS or similar logic simulators * Experience with VHDL, Verilog, C * Experience with SDF back annotated timing functional simulation * Experience with Prime-Time and STA * Work with the library engineers to provide accurate pad library * Work with the Standard cell engineers to provide accurate Verilog modules * Experience with vector processing tools
Job Area: Engineering - Hardware Req #: G1823256 Job Title: Chip Level Thermal/Mechanical/Electrical Analysis Engineer Location: California - San Diego Post Date: 11/11/2008 9:21:38 AM Regular/Temp: R # Positions: 1
Education: Bachelor's degree required, Master's Degree preferred.
$
Role: The candidate will contribute to the development of a 3D Chip integration technology based on Through-Silicon-Via process. The candidate will participate in the characterization, modeling, and simulation activities required for deployment of Design Enablement, including Design Rules, Application Rules, and Electrical and Thermo-Mechanical Models, necessary for deployment of real products. The position requires hands-on simulation and characterization work, and interactive collaboration with both, the process and the design teams. The candidate will also participate in the development of technology infrastructure including definition, design and characterization of calibration and validation test chips and evaluation and assessment of the various possible electro-thermo-mechanical simulation tools and methodologies.
Responsibilities will include: <LI>Perform hands on Electrical - Thermal - Mechanical Simulation analyses <LI>Work with vendors to develop and evaluate electro-thermo-mechanical simulators <LI>Explorations of processes and design space to characterize various technology options <LI>Definition of Rules and Guidelines that define 'safe operating area' for a technology <LI>Definition and extraction of compact Electro-Thermo-Mechanical models <LI>Design of test structures and circuits to support model extraction and validation
Skills: <LI>Understanding of physical thermal and/or mechanical modeling methods and techniques, such as thermo-mechanical finite element modeling and/or compact model extraction <LI>Understanding of the IP/transistor level circuits and simulations (SPICE) environment and associated methodologies <LI>Software skills such as writing scripts to automate use of tools and flows is desirable <LI>BS EE/Physics or ME + 5 to 10 years working experience, or equivalent <LI>Materials, process and device knowledge is desirable <LI>Exposure to digital design methods such as extractions, static timing, etc. is desirable.
Job Area: Engineering - Hardware Req #: E1823275 Job Title: Mechanical Engineer, Sr/Staff Location: California - San Diego Post Date: 12/1/2008 4:29:45 PM Regular/Temp: R # Positions: 1
Education: Bachelor's or Master's degree in Mechanical Engineering.
$
Role: The successful candidate will become a key member of the Corporate Mechanical Engineering department, with a focus on Advanced Technology projects. Responsibilities include researching and creating physical concepts of innovative wireless devices, developing prototypes, engineering refinement, development and protection of intellectual property, and transfer of knowledge for practical utilization. The engineer will interface with internal staff and outside suppliers in the execution of a variety of multi-disciplined projects.
Skills: 10+ years actively involved in developing mobile wireless devices for consumer applications. Possesses a strong understanding of mechanical engineering, with strong accumulated experience in other related areas such as HW, CAD, antenna design, human factors, etc. Strong knowledge in integrating displays, audio components, and other subsystems into a compelling mobile product. Well versed in engineering materials and fabrication methods. Cognizant of industry trends in mobile product design. Translates requirements into development schedules, tasks, and staffing needs. Performs complex analysis, design, and development tasks with a high degree of efficiency. Anticipates, identifies, and solves problems independently. Applies rigorous methodology to design and design optimization. Strong contributor at design reviews and project meetings. Expert level of knowledge in documentation tools and processes. Effectively communicates with project management group and team members Strong written and verbal communication skills are required, including the ability to verbally present technical information to peer groups. Coordinates effectively with various disciplines (SW, HW, Mfgr, Test, CM) during project development. Enthusiastic user of a variety of wireless devices. Understands the information required by an audience and distills the information down to the key points. Self motivated and operates with little direct guidance or supervision. Able to work effectively with incomplete or vaguely defined requirements. Familiar with protection of intellectual property.
Job Area: Engineering - Hardware Req #: G1732909 Job Title: Hardware Engineer - Board Level Digital Hardware Design (Multiple Levels-Positions) Location: California - San Diego Post Date: 10/21/2008 6:58:41 PM Regular/Temp: R # Positions: 5
Education: Required: Bachelor's, Electrical Engineering Preferred: Master's, Electrical Engineering or equivalent experience
$
Role: Develop CDMA phones with the latest QUALCOMM MSMs (Mobile Station Modems), RadioOne RF ICs, and power management devices for smart phone and multimedia applications. Design, analyze, integrate, verify, and maintain digital hardware and circuit card assemblies. You will design platforms that include ultra high performance ARM processor, integrated 3D graphics, streaming video, digital signal processing, ultra-low power consumption, CD quality audio, USB OTG, Bluetooth, GPS, and 802.11.
Responsibilities include board-level digital, power, analog design, analysis, and test. Design and simulate state of the art high density PWB/PCBs. Must be able to quickly assimilate and refine existing phone hardware designs; apply integration and problem solving skills in the lab; read and write specifications and requirements, work closely with software and RF engineers, and actively contribute toward the evolution of our products.
Skills: Multiple positions offered at various levels. Seeking 3-12 years experience. Ideal candidate should have experience in consumer electronics, wireless, or low power design.
Solid understanding of electrical engineering and circuit fundamentals. Strong knowledge of both digital and analog design. Baseband hardware and circuit card design, including digital, analog, and audio. Strong lab skills a plus. Knowledge of transmission lines, cross talk, efficient low-power supply design, decoupling, and layout of high performance digital circuits. FPGA and CPLD design experience. Familiarity with modems, DSPs, microprocessors, memories, LCD's, batteries, voltage regulators, camera sensors, and other consumer electronics hardware. Embedded programming skills. Excellent interpersonal and teamwork skills. Outstanding communications skills, oral and written. Project leadership. Assertive go-getter who gets things done.
Job Area: Engineering - Hardware Req #: G1737329 Job Title: Reliability Development Engineer - Senior Staff Location: California - San Diego Post Date: 10/21/2008 10:45:13 AM Regular/Temp: R # Positions: 1
Education: Master's degree in Electrical Engineering orrequired with Semiconductor Device Physics emphasis. PHD preferred.
$
Role: QCT provides complete chipset solutions and integrated applications from the Launchpad suite of advanced technologies. Our integrated solutions offer device manufacturers reduced bill-of-materials costs, time-to-market, and development time. Mobile handsets powered by QCT chipsets can offer more features while maintaining a smaller, sleeker form-factor and benefiting from reduced power demands.
Successful candidate will participate in cross functional teams supporting design for reliability initiatives in advanced silicon technology nodes. Specific areas include facilitation of technology assessments, reliability risk assessments and mitigation techniques, as well as reliability characterization and initial supplier development. Results will be published and communicated across relevant organizations within the business unit. Major focus will be establishing strong interdepartmental lines of communication to enhance the product development cycle, ensuring robust products which meet or exceed customer expectations.
Skills: Minimum of ten years in current or emerging CMOS,RFCMOS and MEMS silicon technologies. Candidate would have performed initial investigations, team development, reliability analysis and process capability support for potential silicon technology suppliers.Supported emerging technologies, test chip design and evaluation activities. Strong interpersonal communication, written and presentation skills are an important requirement for this position. Facilitated due diligence in the Fab selection processes to include developing and supporting supplier reliability interface and technology investigations. Obtained and assessed foundry technology and test chip design content and analyze results for applicability to product, identify potential reliability/manufacturability issues to product and facilitated reliability mitigation plan development and implementation. Facilitated or contributed to successful cross functional product development teams. Silicon supplier (IDM, Pure Play) Technology and Reliability interface experience including device analysis, process technology integration, Wafer Level Reliability, Process and Product Qualification in the deep sub-micron and nanometer technology nodes. Experience in Design for Reliability methodologies. Exposure to a Fabless environment as well as hands on Fab experience.
Job Area: Engineering - Hardware Req #: G1711950 Job Title: Analog/Digital Mixed Signal IC Design Engineer(s)- San Diego Location: California - San Diego Post Date: 12/1/2008 11:43:18 AM Regular/Temp: R # Positions: 3
Education: Bachelor's Degree in Electrical Engineering required. PhD in Electrical Engineering preferred.
$
Role: QUALCOMM CDMA Technologies (QCT) is the largest provider of 3G chipset and software technology in the world, with chipsets shipped to more than 50 customers and powering the majority of all 3G devices commercially available. QCT partners with nearly 60 3G network operators around the globe and has the largest CDMA engineering team in the wireless industry.
QCT provides complete chipset solutions and integrated applications from the Launchpad suite of advanced technologies. Our integrated solutions offer device manufacturers reduced bill-of-materials costs, time-to-market, and development time. Mobile handsets powered by QCT chipsets can offer more features while maintaining a smaller, sleeker form-factor and benefiting from reduced power demands.
QCT values collaboration with its customers and partners and works closely with them to enable their success. We offer a wide range of tools to support the device development process, and develop new technologies based on the needs and demands of the wireless market. Devices for all market segments can now include features enabled by 3G wireless technology, in demand by a growing and increasingly sophisticated wireless community.
Apply your analog/digital integrated circuit design expertise to the development of mobile communication systems and wired prepherals. Circuits of interest are: A/D & D/A converters, Sigma-Delta Modulators, continuous time and switched-cap filters, Audio CODECs, PLLs, voltage regulators, precision references, USB HS PHY. Low voltage and low power design techniques are emphasized.
Skills: Requires industry experience and/or expertise in both analog transistor-level and digital design in CMOS.
Knowledge of digital signal processing is a plus, as is knowledge of Cadence, Spice, Matlab, verilog or VHDL.
Job Area: Engineering - Hardware Req #: G1712491 Job Title: Analog/Power IC Design Engineer(Senior Levels) - San Diego Location: California - San Diego Post Date: 11/20/2008 9:38:15 AM Regular/Temp: R # Positions: 1
Education: Required: Master's, Electrical Engineering Preferred: Doctorate, Electrical Engineering
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Role: QUALCOMM CDMA Technologies (QCT) is the largest provider of 3G chipset and software technology in the world, with chipsets shipped to more than 50 customers and powering the majority of all 3G devices commercially available. QCT partners with nearly 60 3G network operators around the globe and has the largest CDMA engineering team in the wireless industry.
QCT provides complete chipset solutions and integrated applications from the Launchpad suite of advanced technologies. Our integrated solutions offer device manufacturers reduced bill-of-materials costs, time-to-market, and development time. Mobile handsets powered by QCT chipsets can offer more features while maintaining a smaller, sleeker form-factor and benefiting from reduced power demands.
QCT values collaboration with its customers and partners and works closely with them to enable their success. We offer a wide range of tools to support the device development process, and develop new technologies based on the needs and demands of the wireless market. Devices for all market segments can now include features enabled by 3G wireless technology, in demand by a growing and increasingly sophisticated wireless community.
Apply your analog integrated circuit design expertise to the development of power management integrated circuits for portable battery powered wireless and consumer electronics applications. These devices contain low drop out linear voltage regulators, step up and step down switch mode voltage regulators, battery charge controllers, crystal oscillators, precision references, comparators, audio amplifiers, video amplifiers, precision current sources and high speed data transceivers
Skills: Experience with multiple voltage domain design techniques is essential. Strength in device physics and ultra low power design techniques is a plus. Good lab skills is also essential.<p>Requires 5 years analog transistor-level design industry experience. (BiCMOS, bipolar, CMOS)as well as a knowledge of Cadence or other analog IC design tools.
Job Area: Engineering - Hardware Req #: G1751328 Job Title: PCB Engineer - ATE High Speed Load Board Design Location: California - San Diego Post Date: 11/26/2008 12:00:04 AM Regular/Temp: R # Positions: 1
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